Specification-based trace analysis is a topic of particular interest due to the many different logics and supporting tools that have been developed over the last decade, including the following to just mention a few.
Other forms of RV, not treated in this paper, include for example algorithm-based trace analysis, such as detecting concurrency issues such as data races and deadlocks specification mining from traces and trace visualization. This paper focuses specifically on specification-based trace analysis, where execution traces are verified against formal specifications written in formal logical systems. The core idea is to instrument a program to emit events during its execution, which are then processed by a monitor.
Runtime verification, Footnote 1 from here on referred to as RV, refers to a class of lightweight scalable techniques for analysis of execution traces.